A sample-and-hold module operates periodically, under the control of a clock, according to two alternating phases: the first phase is the sampling phase during which a voltage level of an input signal (notably an analog signal that one wishes to convert into digital) is stored in a storage capacitor; the second phase is the hold phase, during which the sampled voltage, that is to say the voltage stored in the capacitor, is maintained at its value, doing so for the entire time necessary for the operations done downstream of the sample-and-hold module. Typically, in an application to an analog-digital converter, it is known that the analog-digital conversion operation takes a certain time and the hold phase maintains the sampled voltage level throughout the entire time necessary for the conversion, before passing to a following sampling phase and to a following conversion.
Among the qualities expected of a sample-and-hold module, there is notably speed of operation, accurate copying of the input voltage into the storage capacitor, and lossless conservation of the voltage stored in the storage capacitor for the duration of the hold time.
FIG. 1 represents a sample-and-hold module of the prior art which exhibits good characteristics from this point of view but which has been found to possibly exhibit a troublesome defect to which we will return later.
The sampler of FIG. 1 is intended to sample an input voltage Vin. It essentially comprises a pair of differential branches forming a unit-gain buffer amplifier intended to avoid unnecessarily loading the upstream circuit which produces the voltage Vin. The differential pair comprises two identical transistors T1 and T2 whose emitters are joined and linked to a constant current source (of value 2.I0), the base of the transistor T1 receiving the voltage Vin. The collector of the transistor T1 is linked to a supply voltage Vcc. The collector of the transistor T2 is supplied by this voltage Vcc but through a current source which imposes a current I0 (half of the former) in the transistor T2. The transistor T2 is arranged as a diode, that is to say its collector is linked to its base.
This arrangement permits the voltage on the base of T2 to reproduce the input voltage Vin exactly. Indeed, the current in the collector of T1 is equal to I0, like that of T2, since the current 2.I0 is shared between a current I0 in T2 and a complementary current 2I0-I0 in T1. The base-emitter voltages are therefore the same and the base voltage of T2 takes the value of that of T1.
The base of the transistor T2 is connected to the base of a follower transistor T3 which has two functions depending on whether the sampler is in sampling mode or in hold mode.
In sampling mode, the transistor T3 is biased as a voltage follower by a transistor T4 which applies an outgoing current to its emitter. Its emitter voltage then follows the variations of its base voltage, with an offset of a base-emitter voltage Vbe. The emitter of T3 is linked to the storage capacitor Cech and this capacitor therefore takes the value of Vin to within the offset Vbe. The offset is constant and therefore it does not pose a problem; it poses still less of a problem in a differential system where a differential voltage Vin+−Vin− would be sampled with two assemblies like that of FIG. 1; the output voltage is then the difference between the voltages stored on the capacitors; the offset Vbe disappears in this subtraction.
In hold mode, the transistor T3 is disabled by a transistor T5 which lowers the base potential of T3 and tends to extract a negative current from its base.
The transistor T4 and the transistor T5 are turned on alternately by complementary clock signals HE (which turns on T5) and HB (which turns on T4); these complementary signals define the sampling phase and the hold phase respectively.
Finally, a hold maintaining circuit, CLMP, applies to the base of the transistor T3, during the hold phase, a voltage which substantially copies over the voltage present on the storage capacitor, so that the base-emitter voltage of T3 remains in the vicinity of zero during the hold phase. It thus prevents the base-emitter voltage of T3 from descending too low, which would tend to saturate the transistor T5, slowing down the return to the sampling mode; it also maintains a base-emitter voltage of T3 constant, independent of the input voltage Vin.
The output of the sampler is tapped off from the capacitor Cech, preferably after a buffer amplifier AMP of unit gain and high input impedance.
FIG. 2 represents a chart of the signals observed during the operation of the sample-and-hold module under the assumption that the signal Vin to be converted is nearly sinusoidal. The clock signal HB is visible in the central part of the chart. The signal HB is the complement of the signal HE. The voltage Vech across the terminals of the storage capacitor is visible in the lower part of FIG. 2. During the sampling phases (HE at the high level, HB at the low level, the voltage Vech follows the evolution of the voltage Vin. During the hold phase (HE at the low level, HB at the high level), the voltage Vech remains pegged at the value that it had at the end of the sampling period.
However, very significant negative transition spikes are also observed at the end of the hold period, before the voltage Vech starts to follow the evolution of the voltage Vin again. These spikes do not prevent the basic operation of the sample-and-hold module: throughout the hold phase, the voltage level Vech is stable and the circuits which are downstream (for example an analog-digital converter) can use it. However, if they are of too significant an amplitude, they may have an effect on these downstream circuits: for example, if a differential amplifier such as AMP is placed directly downstream, it may be saturated by the negative spike, the effect of this being to greatly slow down the re-establishment of its output voltage at the time of the sampling phase. At high frequency, the amplifier runs the risk of not being able to follow the variations of Vin because of its recovery time, and the sampling voltage Vech will not be correct.
It has been found that these switching spikes could be due mainly to the fact that, when passing to the sampling phase, the transistor T3 turns on more quickly than the transistor T2: both were disabled by the turning on of the transistor T5; they turn on as a result of the disabling of the transistor T5 and, as regards the transistor T3, as a result of the turning on of the transistor T4. The disabling voltage present on the base of T3, applied by the hold maintaining circuit CLMP, is also found on the sampling capacitor and produces a negative spike since, as has been seen, this voltage is always lower than that of the sampling capacitor. This spike disappears as soon as the base of the transistor T3 takes the new value of the input voltage Vin.